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IP Cores

In addition to the IP cores that provide the bridge between the user application and external interfaces, applications typically make use of IP cores for specific signal processing functions such as Fast Fourier Transforms (FFTs) or Finite Impulse Response (FIR) filters. These IP cores are analogous to library calls in the software domain, providing a high-level interface between the application and the underlying processing hardware.

For high-performance embedded computing, most IP cores follow a streaming I/O model, providing FIFO-based input and output streams with a separate control port. Sensor data is presented to the input FIFO and clocked into the core; after a given number of clock cycles, results are available at the output FIFO. Typically, the width of the FIFO i! s selectable at compile time, and often the signal processing parameters (FFT window size, for example) are dynamically configurable at runtime to support adaptive algorithms.

The internal implementation of an FFT core can be optimized for speed or for resources, with tradeoffs between the two. Higher speed is typically achieved through more parallelization, which consumes more resources.

Parallelization is driven by how many resources the function consumes relative to how many resources are available in the device. Virtex-5 offers advantages in the internal implementation through the use of higher-performance DSP slices and multiply-accumulate primitives. For some functions, these embedded device features can be used instead of synthesized logic, reducing the number of logic slices needed for a given level of parallelization.

Finally, Virtex-5 devices offer higher gate counts per device, and perhaps more importantly, higher density for a given power limit! . Between the overall density improvement and the use of embedded features, a given implementation can either maintain the same degree of parallelism - and fit more functions into the chip - or increase the parallelism and achieve higher performance.

From the user's perspective, the end result of all of the above tradeoffs is simply that the internal performance of the FFT core is faster, with more tradeoffs available between speed and resources. The semantics of the interface to the FFT core, and therefore the use of the core by the user's firmware, does not change from device to device. This enables the user to easily migrate their internal firmware from Virtex-II Pro to Virtex-5 without redeveloping other modules.


 
 
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 Migrating to Virtex-5
 
A large number of signal processing systems today use Xilinx Virtex-II Pro FPGA technology. The Virtex-5 family offers significant improvements in density, power, and speed, all of which are critical for both current and future applications. Migration of existing user applications - both software and firmware - to next-generation products using Virtex-5 will extend the capability and service life of existing systems and create better solutions for end users when the migration is successfully managed.
 
 
It's All About the Developer's Kit
 
To support migration from product to product, whether from PMC modules to XMC modules, from VXS to VITA 46 (VPX), or from Xilinx Virtex-II Pro to Virtex-5, the definition of the interfaces and the flexibility of the IP cores provided in the Developer's Kit (DK) are the most critical factor. If the DK performs well, the underlying hardware can improve with technology, but the user's investment in their application IP and software is protected through the interfaces provided by the DK.

DK's for Tekmicro's VXS products typically contain IP cores for the followin! g functions:

·    A/D interfaces
·    Memory controllers (DDR, SRAM)
·    QuixStart bitstream management
·    QuixStream interconnect, using either Aurora, GbE, or VITA 55 Virtual Streaming Protocol
·    JazzStore SoC data recorder module (as an optional component)

Each of the above IP cores presents an abstract interface to the hardware that supports migration from existing Virtex-II Pro based products to future Virtex-5 platforms with minimal application changes. The following discussion will focus primarily on the JazzStore SoC core as an example, but the discussion applies equally to all of the above functions.

 
 
JazzStore System-on-Chip (SoC) core
 
By maintaining the same interface to the user application, the core provides a "black box" capability that encapsulates the changes between Virtex-II Pro and Virtex-5. Using the JazzStore SoC users can migrate their design to newer technology without design or architecture changes.

 v2 to v5

The external interface uses a Xilinx RocketIO SerDes to implement a 2.125 Gbps Fibre Channel interface. The RocketIO module provides the serializer-deserializer, 8B/10B encoder, and phase locked loop clock circuit to implement the Fibre Channel FC.1  interface between the core and the external fiber optic transceiver.

The core then uses dedicated logic to implement the FC.2 state machines and framing to stream data between the on-chip 405 PowerPC processor and the external interface. The software running in the PowerPC implements the appropriate higher-level protocols along with file and session management and the Windows-compatible FAT32 file system. The core reuses the DDR memory controller from the DK to provide buffering of the data stream and of file system data structures.

To the user, the core appears as a simple FIFO interface with a separate contro! l port to manage record sessions and other out-of-band control and status activity. While the internals of the core utilize the RocketIO and PowerPC resources, from the user perspective the implementation simply streams data to disk. The type of disk (single drive, RAID, or JBOD) and the management of the file system are all handled within the core. This provides a level of abstraction that supports the goal of easy migration from Virtex-II Pro to Virtex-5 without changing the user application.


For a complete information on all of TEK Microsystems products, contact us directly. For complete product information visit tekmicro.com.

 
 
Summary

The use of FPGA processors for high performance signal processing is widely recognized as the best choice for implementing streaming processing solutions with severe size, weight and power constraints due to the raw performance of FPGAs for repetitive calculations.

Migration of user applications from Virtex-II Pro to Virtex-5 is ultimately driven by the performance of the signal processing functions being undertaken within the FPGA. The use of IP cores wi! th well-defined boundaries helps make migration successful for the "utility" functions such as memory, I/O, recording, and communications. Signal processing functions can also benefit from the same techniques. Many applications will be transportable from Virtex-II Pro to Virtex-5 through the use of new IP cores such as the JazzStore SoC and a simple recompile of the user application with a new DK.

For the complete article visit Migrating to V5