The biggest benefit of using FPGAs in sensor processing systems is the ability to implement typical signal processing functions very efficiently and with very high performance. FPGAs achieve this by implementing many arithmetic operators in parallel on a single device. For example, the Quixilica QR decomposition core, can be implemented with more than 140 floating point arithmetic operators (a mixture of adder/subtractors, multipliers and dividers), and the core can be clocked at speeds in excess of 150 MHz, providing a sustained arithmetic rate of over 20 GFLOPS, while dissipating approximately 25 W. By comparison, the performance of a contemporaneous Intel Pentium CPU implementing the same algorithm is 4 GFLOPS and 70 W. The challenge with FPGA designs of this type is the design of efficient control and data scheduling, in order to ensure that each arithmetic operator carries out a useful operation on every clock cycle. However, once an efficient design has been achieved for a particular signal processing function, this can be encapsulated as an "IP Core" which can be re-used in many designs. There are many vendors offering IP cores to implement a wide range of DSP building blocks.

The front-end signal processing functions typical of the front-end of many sensor processing systems lend themselves ideally to implementation in an FPGA. They are characterized by relatively simple control structures, highly repetitive arithmetic operations, and, in many cases, relatively little storage of intermediate results. FIR filtering, digital down-conversion, and FFTs are good examples of this type of operation. In a recent application which made extensive use of FFTs to analyze the spectrum of multi-channel sensor data, the FFT was ported from a conventional CPU-based architecture (using VME 64-based quad-PowerPC cards) to a VITA 41, FPGA-based architecture in which the FPGA was located on the same card as the ADCs which digitized the analog sensor data. It was possible to implement the whole of the FFT-intensive preprocessing on a single FPGA, eliminating ten quad-PowerPC cards from the system.

In order to illustrate the benefits of VITA 41 and FPGAs for implementing sensor processing systems, consider the following example of a phased-array radar application. The system uses four antenna channels, with analog receiver and down-conversion providing an intermediate frequency of 1 GHz bandwidth. This is digitized directly using four 10-bit, 2 GSPS ADCs, located on two VITA 41 payload cards. Each ADC produces a data rate of 20 Gbit/s, so the aggregate data rate for the pair of channels on a payload card is 40 Gbit/s or 5 GByte/s, orders of magnitude greater than current VME systems can support, but only twice the available VXS bandwidth of the payload slot. It is therefore necessary to reduce the data rate by pre-processing the data on the payload card. This is done within an FPGA on each digitizer card. In this case, the preprocessing consists of digital down-conversion, followed by decimation in the data rate by a factor of 8, which reduces the data rate to 5 Gbit/s, which is within the VXS payload bandwidth.

The channel data is transmitted to an FPGA-based processing card located in the VXS switch slot. Here, the data from all four channels is combined using adaptive beamforming. The beamforming operation is a simple spatial filter - a set of complex multipliers followed by an adder tree. The adaptive coefficient calculation is carried out using QR decomposition, with the channel data being buffered in memory while the coefficients are calculated. The switch slot is an ideal position in the VXS architecture in which to implement the beamforming operation, because beamforming requires data from all of the channels. The adaptive weight calculation operation is highly computationally intensive, however the use of an FPGA-based processor in the switch slot enables the operation to be carried out within a single card, removing the need to distribute the algorithm and the data across an array of CPU or DSP cards. This in turn considerably simplifies the system architecture.

The adaptive weight calculation is implemented in a single FPGA, with the coefficients passed to a second FPGA in order to apply them in the beamformer. The whole architecture is highly scalable, and further antenna channels can be added to improve the beamforming capability, which will in turn increase target detection and interference rejection capability. Further digitizer cards may be added to the system, with the VXS backplane supporting up to 18 payload cards.

Within the front-end pre-processing as just described, the high-speed serial interconnections across the VXS backplane are implemented using Aurora, a lightweight, open protocol developed by Xilinx. This is possible because both ends of the communication links are implemented using FPGAs, so they are under control of the developer. The output from the front-end pre-processing, consisting of one or more data streams representing spatially-formed beams are transmitted to other subsystems for subsequent processing, using a standard protocol such as Infiniband, Gbit Ethernet, etc, to take advantage of standard commercially available networking components.

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Summary

Military sensors will continue to require the latest processing and interconnection strategies to meet an ever increasing processing burden. Algorithm complexity and thus processing intensity will continue to increase, but with standards such as VITA 41, a new range of development options are now available to the designer. The combination of FPGAs and high bandwidth interconnections enabled through VITA 41 can provide solutions to system requirements that were previously considered unfeasible.

The Quixilica VXS cards are examples of VITA 41 FPGA cards and one possible implementation of the application example described in this paper uses the Quixilica Neptune VXS-1 digitizer and the Callisto VXS-1 processing and switch cards. Neptune provides two 2-GSPS 10-bit digitizer channels, with a Virtex-II Pro P70 FPGA and DDR memory, and Callisto implements 5 Virtex-II Pro P50 FPGAs each with DDR SDRAM. Using high bandwidth interconnection protocols such as Xilinx Aurora, enables distribution of data to the appropriate FPGA processing platform such as from Neptune to Callisto, if the example architecture is considered, facilitating the implementation of the required processing chain. Using FPGA technology not only makes the system feasible but also significantly reduces the SWAP compared to architectures based around DSPs or CPUs.

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Founded in 1981 and headquartered in Chelmsford, Massachusetts, TEK Microsystems, Inc., designs, manufactures and markets a wide range of advanced high-performance boards and systems for embedded real-time data acquisition, data conversion, storage and recording systems. Tekmicro's comprehensive product line includes intelligent carrier boards based on widely adopted industry standards and more than 30 I/O modules. The Company provides both commercial and rugged grade products. These products are used in real-time systems designed for customer applications such as reconnaissance, electronic warfare, signals intelligence, mine detection, medical imaging, radar, sonar, semiconductor inspection and seismic research.

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