In an embedded system built with FPGA resources, it is possible to utilize the Multi Gigabit Transceiver (MGT) and embedded processor components to realize a very efficient interface to a hard disk system (e.g. Fibre Channel disk or RAID system). This allows a complete data storage system to potentially be built as part of the FPGA firmware within the embedded system with little additional hardware required apart from the actual disk system itself. FPGAs such as the Virtex-II Pro contain multiple MGT resources, making it feasible to implement multiple parallel links to a number of disks or RAID systems to scale available data recording bandwidth if required.

All of this can be achieved within a single physical chip, alongside other system functionality such as digital signal processing if required. Using the FPGA to implement the storage interface offers considerable size, cost and system reliability benefits. A second level of scalability is possible by employing multiple FPGA devices in a system, each with multiple links to multiple disk systems, to further improve the aggregate data storage bandwidth available.

Because the data recording functionality resides in firmware on the FPGA, it is easier to tailor the recording system to dovetail exactly with the requirements of the specific application within which it is deployed.

Serial FPDP to Fibre Channel Storage

In this example, the complete system is implemented using a single FPGA device (e.g. Xilinx Virtex II Pro P50), equipped with 4 fiber-optic transceivers to convert the high speed serial signals from the MGTs in the FPGA to fibre.

Firmware in the FPGA is used to provide the following functionality:

- Implementation of Serial FPDP protocol. Manages conversion of the serial data received from the fiber-optic transceiver back to a simple parallel data stream.

- Optional, high speed processing of data stream. This might typically be a signal processing function such as a down conversion operation or a Fourier transform.

- Interfaces to Fibre Channel Disk / RAID. This part of the firmware is responsible for all of the management and control required to interface the FPGA directly to a Fibre Channel RAID or hard disk.

- FIFO interface Data to be recorded or played back is streamed via a port with a simple FIFO style interface. A FIFO of sufficient depth is provided to allow the respective data rates and access patterns of the SFPDP interfaces and the Fibre Channel disk interfaces to be matched.

The availability of multiple MGT resources inside the FPGA allows implementation, in this case, of two SFPDP and two Fibre Channel interfaces, effectively doubling the data throughput of the system.

The Fibre Channel interface implementation takes advantage of the availability of the embedded Power PC cores in the FPGA to implement the complex control and management logic required for the Fibre Channel protocol and the filing system on the disk. The FPGA implementation allows the processor to be used to manage the non-time critical, yet complex operations required to manage the system whilst simultaneously providing dedicated, customized hardware data paths to allow the time critical real time data to be streamed directly to and from the disk systems.

This optimal combination of resources in the FPGA yields a complete system-on-chip solution that is extremely compact yet sufficiently powerful to support real time data recording from multiple Serial FPDP data sources.

The TEK Microsystems Jazzstore SOC technology offers an FPGA implementation of a Fibre Channel based data recording system. The Jazzstore SOC technology complements the Tekmicro Jazz and Quixilica FPGA based hardware product ranges, allowing provision of real time data record / playback functionality in a wide range of demanding real time applications.

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