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Boundary-scan Review

A newsletter brought to you by JTAG Technologies - February 2009

CONTENTS

Clue Corner: Attach notes to your development project
Upcoming Standard IEEE 1149.7
Product Update: CD14 packed with new features
New embedded flash programming tools available
Expanding test access with JT 2149/MPV

The new "dot 7" standard, IEEE 1149.7 Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture, is a superset of the broadly supported IEEE 1149.1. IEEE 1149.7 adds considerable functionality to the existing standard. It defines system-level boundary-scan architecture for Systems-on-Chip (SoC) devices in a manner that is fully compatible with the underlying 1149.1 standard. In addition to its treatment of SoCs, IEEE 1149.7 reduces the TAP port pin count from four down to two. For systems that integrate multiple ICs, reducing the number of pins and traces will help designers add more functional pins and/or lower package costs. JTAG Technologies continues its track record of fully supporting all boundary-scan standards. This support will extend to IEEE 1149.7 after it is officially ratified; which is scheduled for 1Q2009. For more information on our support of IEEE standards, please refer to the standards section on our website.

In each issue we highlight a DFT technique or product capability to help you get the most benefit from our boundary-scan technology. We hope you find it interesting and useful.

Attach notes to your development project.

Avoid retracing your steps.

As most engineers know, detailed documentation is vital for maintaining a project through its lifecycle. A boundary-scan project is no different. Consider a project developed several months ago for which you receive an Engineering Change Order (ECO). You open the project only to discover several manually entered constraints or configurations, the reason for which, you cannot recall. Alternatively, it is possible the project has become the responsibility of another engineer or project team. For this reason, JTAG ProVision is equipped with the capability to add "Notes" to a project.

Developers may add Notes describing the purpose of constraints they've placed on individual nets. Notes are generated by JTAG ProVision to describe automatically set constraints derived from device models and design information. Notes can also be added at the application-level providing high-level details about the design.

We welcome your tips or techniques for future issues. Submit your ideas and if we publish it we'll send you a special "thank you" gift.

Take advantage of enhanced functionality and support now available on CD14. JTAG ProVision and JTAG Visualizer are among the updated products with this release, sent free-of-charge to all users with current maintenance contracts. Here is a sampling of the new features you'll find:

JTAG ProVision

Buffer and multiplexer support for memory testing expands coverage for boundary-scan applications.
Password control for the integrated sequencing. Users with different credentials can now use built-in application execution features.
Expanded model library now has more than 4,650 non-boundary-scan device families; covering more than 28,500 different devices.

JTAG Visualizer

Flip and rotate views allow users to "see" the board in different orientations; flipping it over to see the bottom side or rotating it for increased clarity.
Worldview, a small window that shows layout or schematic views on a small scale. When a user zooms in, a small rectangle in the worldview indicates which part of the board or schematic is displayed in the "normal view". The small rectangle is moved to view another part of the board or schematic.

JTAG Technologies continues to grow its offering of programming tools for controllers with embedded flash. Just released tools include one that supports the DSP-TMS320F28xx family from Texas Instruments and another for the Freescale MPC565 PowerPC. Check our website for a detailed list of the programming support we offer for other devices from TI, Freescale, ST Microelectronics, Philips, and more.

JT2149/MPV is the latest addition to our line of Digital I/O Scan (DIOS) modules. It expands test access to PCBs that require external I/O stimulus and response monitoring and is slot compatible with our QuadPOD^TM transceiver system. This MPV (multi-programmable voltage) DIOS module enhances regular interconnect testing by exercising the board connections in synchronization with the boundary-scan infrastructure. The JT2149/MPV also features the new SCIL^TM (Scan Configurable Interface Logic) technology that JTAG Technologies developed to allow custom functions such as pattern generators, counters and bus simulators to be factory-formatted for advanced functional and pattern-oriented testing. View the press release for more information.